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1 fn8128.4 x5163, x5165 cpu supervisor with 16kbit spi eeprom description these devices combine four popular functions, power-on reset control, watchdog timer , supply voltage supervision, and block lock protect seri al eeprom memory in one package. this combination lo wers system cost, reduces board space requirements, and increases reliability. applying power to t he device activates the power-on reset circuit which holds reset /reset active fo r a period of time. this allows the power supp ly and oscillator to stabilize before the processo r can execute code. the watchdog timer provides an independent protection mechanism for microcontroller s. when the microcontroller fails to restart a timer within a selectable time out interval, the device activates the reset /reset signal. the user selects the interval from three prese t values. once selected, the interval does not change, e ven after cycling the power. the devices low v cc detection circuitry protects the users system from low voltage conditi ons, resetting th e system when v cc falls below the minimum v cc trip point. reset /reset is asserted until v cc returns to proper operating level and stabilizes. five industry standard v trip thresholds are available, however, intersils unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. features ? selectable watchdog timer ?low v cc detection and reset assertion - five standard reset threshold voltages - re-program low v cc reset threshold voltage using special progra mming sequence - reset signal valid to v cc = 1v ? determine watchdog or low vo ltage reset with a volatile flag bit ? long battery life with low power consumption - <50a max standby c urrent, watchdog on - <1a max standby current, watchdog off - <400a max active current during read ? 16kbits of eeprom ? built-in inadverten t write protection - power-up/power-down protection circuitry - protect 0, 1/4, 1/ 2 or all of eeprom array with block lock ? protection - in-circuit programmable rom mode ? 2mhz spi interface modes (0,0 & 1,1) ? minimize eeprom programming time - 32-byte page write mode - self-timed write cycle - 5ms write cycle time (typical) ? 2.7v to 5.5v and 4.5v to 5.5v power supply operation ? available packages: 14 ld tssop, 8 ld soic, 8 ld pdip ? pb-free plus anneal available (rohs compliant) pinouts 8 ld soic/pdip cs/wdi wp so 1 2 3 4 reset /reset 8 7 6 5 v cc 14 ld tssop so wp v ss 1 2 3 4 5 6 7 reset /reset sck si 14 13 12 11 10 9 8 nc v cc nc x5163, x5165 v ss sck cs/wdi nc nc nc nc si x5163, x5165 x5163, x5165 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2005, 2006, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn8128.4 august 13, 2015 submit document feedback ordering information part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range temp range (c) package (rohs compliant) pkg. dwg. # x5163pz (note) x5163p z x5165pz (note) x5165p z 4.5-5.5 4.25-4.5 0 to 70 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8z) (no longer available or supported) x5163piz (note) x5163p z i x5165piz (note) x5165p z i -40 to 85 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8iz) (no longer available or supported) x5163s8z* (note) x5163 z x5165s8z* (note) x5165 z 0 to 70 8 ld soic mdp0027 (no longer available or supported) x5163s8iz* (note) x5163 z i x5165s8iz* (note) x5165 z i -40 to 85 8 ld soic mdp0027 (no longer available or supported) x5163v14* x5163v x5165v14* x5165v 0 to 70 14 ld tssop m14.173 (no longer available or supported) (no longer available or supported) x5163pz-2.7 (note) x5163p z f x5165pz-2.7 (note) x5165p z f 2.7-5.5 2.55-2.7 0 to 70 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8z-2.7) (no longer available or supported) x5163piz-2.7 (note) x5163p z g x5165piz-2.7 (note) x5165p z g -40 to 85 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8iz-2.7) (no longer available or supported) x5163s8z-2.7* (note) x5163 z f x5165s8z-2.7* (note) x5165 z f 0 to 70 8 ld soic mdp0027 (no longer available or supported) x5163s8iz-2.7* (note) x5163 z g x5165s8iz-2.7* (note) x5165 z g -40 to 85 8 ld soic mdp0027 (no longer available or supported) x5163pz-2.7a (note) x5163p z an x5165pz-2.7a (note) x5165p z an 2.7-5.5 2.85-3.0 0 to 70 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8z-2.7a) (no longer available or supported) x5163piz-2.7a (note) x5163p z ap x5165piz-2.7a (note) x5165p z ap -40 to 85 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8iz-2.7a) (no longer available or supported) x5163, x5165
3 fn8128.4 august 13, 2015 submit document feedback x5163s8z-2.7a* (note) x5163 z an x5165s8z-2.7a (note) x5165 z an 2.7-5.5 2.85-3.0 0 to 70 8 ld soic mdp0027 (no longer available or supported) x5163s8iz-2.7a (note) x5163 z ap x5165s8iz-2.7a (note) x5165 z ap -40 to 85 8 ld soic mdp0027 (no longer available or supported) x5163pz-4.5a (note) x5163p z al x5165pz-4.5a (note) x5165p z al 4.5-5.5 4.5-4.75 0 to 70 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8z-4.5a) (no longer available or supported) x5163piz-4.5a (note) x5163p z am x5165piz-4.5a (note) x5165p z am -40 to 85 8 ld pdip** mdp0031 (no longer available, recommended replacement:x5163s8iz-4.5a) (no longer available or supported) x5163s8z-4.5a (note) x5163 z al x5165s8z-4.5a (note) x5165 z al 0 to 70 8 ld soic mdp0027 (no longer available or supported) x5163s8iz-4.5a (note) x5163 z am x5165s8iz-4.5a (note) x5165 z am -40 to 85 8 ld soic mdp0027 (no longer available or supported) *add "t1" suffix for tape and reel. **pb-free pdips can be used for through hole wave solder proces sing only. they are not intended fo r use in reflow solder proce ssing applications. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 10 0% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range temp range (c) package (rohs compliant) pkg. dwg. # x5163, x5165
4 fn8128.4 august 13, 2015 submit document feedback block diagram watchdog timer reset data register command decode & control logic si so sck cs /wdi v cc reset & watchdog timebase power-on and generation v trip + - reset /reset reset low voltage status register protect logic 4k bits 4k bits 8k bits eeprom array watchdog transition detector wp x5163 = reset x5165 = reset v cc threshold reset logic pin (soic/pdip) pin tssop name function 1 1 cs/wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvol atile write cycle is underway, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. p rior to the start of any operation after power-up, a high to low transition on cs is required watchdog input. a high to low transition on the wdi pin restarts the watchdog timer. t he absence of a high to low transition within the watchdog ti me out period results in reset /reset going active. 22so serial output. so is a push/pull serial data output pin. a rea d cycle shifts data out on this pin. the falling edge of the serial clo ck (sck) clocks the data out. 36wp write protect. the wp pin works in conjunction with a nonvolatile wpen bit to lock the setting of the watchdog timer control and the memory write protect bits . 47v ss ground 58si serial input. si is a serial data input pin. input all opcodes, byte address es, and memory data on this pin. the rising edge of the serial clock (sck) latches the inpu t data. send all opcodes (table 1), addresses and data msb first. 69sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or data bits present on the si pin. the falling edge of sck changes the data output on the so pin. 7 13 reset / reset reset output . reset /reset is an active low/high, open drain output which goes acti ve whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 200ms. reset /reset goes active if the watchdog timer is enabled and cs remains either high or low longer than the selectable watchdog time out period. a falling edge of cs will reset the watchdog timer. reset /reset goes active on power- up at 1v and remains active for 200ms after the power supply st abilizes. 814v cc supply voltage 3-5,10-12 nc no internal connections x5163, x5165
5 fn8128.4 august 13, 2015 submit document feedback principles of operation power-on reset application of power to the x5 163, x5165 activates a power- on reset circuit. this circuit go es active at 1v and pulls the reset /reset pin active. this signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabiliza tion of the oscillator. when v cc exceeds the device v trip value for 200ms (nominal) the circuit releases reset /reset, allowing th e processor to begin executing code. low voltage monitoring during operation, the x51 63, x5165 monitors the v cc level and asserts reset/reset if supply voltage falls below a preset minimum v trip . the reset/reset signal prevents the microprocessor from oper ating in a power fail or brownout condition. the reset/reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit m onitors the microprocessor activity by monitoring the w di input. the microprocessor must toggle the cs /wdi pin periodically to prevent a reset /reset signal. the cs /wdi pin must be toggled from high to low pri or to the expiration of the watchdog time out period. the state of tw o nonvolatile control bits in the status register determine the watchdog t imer period. the microprocessor can chan ge these watchdog bits, or they may be locked by tying the wp pin low and setting the wpen bit high. v cc threshold reset procedure the x5163, x5165 has a standard v cc threshold (v trip ) voltage. this value will not c hange over normal operating and storage conditions. however, in applications where the standard v trip is not exactly right, or for higher precision in the v trip value, the x5163, x5 165 threshold may be adjusted. setting the v trip voltage this procedure sets the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure directly makes the change. if the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold to the v cc pin and tie the cs /wdi pin and the wp pin high. reset and so pins are left unconnected. then apply the programming voltage v p to both sck and si and pulse cs /wdi low then high. remove v p and the sequence is complete. resetting the v trip voltage this procedure sets the v trip to a native voltage level. for example, if the current v trip is 4.4v and the v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the vo ltage to a lower value. to reset the v trip voltage, apply a voltage between 2.7 and 5.5v to the v cc pin. tie the cs /wdi pin, the wp pin, and the sck pin high. reset and so pins are left unconnected. then apply the programming voltage v p to the si pin only and pulse cs /wdi low then high. remove v p and the sequence is complete. sck si v p v p cs figure 1. set v trip voltage sck si v cc v p cs figure 2. reset v trip voltage x5163, x5165
6 fn8128.4 august 13, 2015 submit document feedback v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip C desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 50mv) execute sequence reset v trip new v cc applied = old v cc applied - error error > -emax error < emax yes no error > emax emax = maximum desired error figure 3. v trip programming sequence flow chart 1 2 3 4 8 7 6 5 x5163, x5165 v trip adj. program nc nc v p reset v trip test v trip set v trip nc reset 4.7k 4.7k 10k 10k + figure 4. sample v trip reset circuit x5163, x5165
7 fn8128.4 august 13, 2015 submit document feedback spi serial memory the memory portion of the dev ice is a cmos serial eeprom array with intersils block loc k protection. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersils proprietary direct write ? cell, providing a minimu m endurance of 100, 000 cycles and a minimum data retention of 100 years. the device is desi gned to interface directly with the synchronous serial peripher al interface (spi) of many popular microcontroller fami lies. it contains an 8-bit instruction register that is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the en tire operation. all instructions (table 1), addresses and data are transferred msb first. data input on the si line is latched on the first rising edge of sck after cs goes low. data is output on the so line by the falli ng edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. write enable latch the device contains a write e nable latch. thi s latch must be set before a write operat ion is initiated. the wren instruction will set the latch and the wrdi instruction will reset the latch (figure 7). this latch is a utomatically reset upon a power-up condi tion and after the completion of a valid write cycle. status register the rdsr instruction prov ides access to the status register. the status register may be read at any time, even during a write cycle. the stat us register is formatted as follows: the write-in-progress (wip) bit is a volatile, read only bit and indicates whether the dev ice is busy wit h an internal nonvolatile write oper ation. the wip bit is read using the rdsr instruction. when set to a 1, a nonvolatile write operation is in progress. when se t to a 0, no write is in progress. 7 65 43210 wpen flb wd1 wd0 bl1 bl0 wel wip table 1. instruction set instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operation s) sflb 0000 0000 set flag bit wrdi/rflb 0000 0100 reset the write enable latch/reset flag bit rdsr 0000 0101 read status register wrsr 0000 0001 write status register (watchdog,blocklock,wpen & f lag bits) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address note: *instructions are shown m sb in leftmost position. instruct ions are transferred msb first. table 2. block protect matrix wren cmd status register device pin block block status register wel wpen wp# protected block unprotected block wpen, bl0, bl1, wd0, wd1 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable x5163, x5165
8 fn8128.4 august 13, 2015 submit document feedback the write enable latch (wel) b it indicates the status of the write enable latch. when wel = 1, the latch is set high and when wel = 0 the latch is reset low. the wel bit is a volatile, read only bit. it can be set by the wren instruction and can be reset by the wrds instruction. the block lock bits, bl0 and b l1, set the leve l of block lock protection. these nonvolatile bits are programmed using the wrsr instruction and allow the user to protect one quarter, one half, all or none of the e eprom array. any portion of the array that is block lock p rotected can b e read but not written. it will remain protected until the bl bits are altered to disable block lock protection of that portion of memory. the watchdog timer bits, wd0 and wd1, select the watchdog time out period. these nonvolatile bits are programmed with the wrsr instruction. the flag bit shows the status of a volatile latch that can be set and reset by the system using t he sflb and rflb instructions. the flag bit is a utomatically reset upon power- up. this flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure. the nonvolatile wpen bit is programmed using the wrsr instruction. this bit works in conjunction with the wp pin to provide an in-circuit program mable rom function (table 2). wp is low and wpen bit programmed high disables all status register write operations. in circuit programmable rom mode this mechanism protects the block lock and watchdog bits from inadvertent corruption. in the locked state (programmable rom mode) the wp pin is low and the nonvolatile bit wpen is 1. this mode disables nonvolatile writes to the devices status register. setting the wp pin low while wpen is a 1 while an internal write cycle to the status register is in progress will not stop this write operation , but the operation disables subsequent write attempts to the status register. status register bits array addresses protected bl1 bl0 x516x 0 0 none 0 1 $0600-$07ff 1 0 $0400-$07ff 1 1 $0000-$07ff status register bits watchdog time out (typical) wd1 wd0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled status register bits watchdog time out (typical) wd1 wd0 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 654321 0 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0 figure 5. read eeprom array sequence x5163, x5165
9 fn8128.4 august 13, 2015 submit document feedback when wp is high, all functions, including nonvolatile writes to the status register operate normally. setting the wpen bit in the status reg ister to 0 blocks the wp pin function, allowing writes to the status register when wp is high or low. setting the wpen bit to 1 while the wp pin is low activates the progr ammable rom mode, thus requiring a change in the wp pin prior to subsequent status register changes. this allows manufacturing to install the device in a system with wp pin grounded and still be able to program the status regist er. manufacturing can then load configuration data, manufacturing time and other parameters into the eepr om, then set the portion of memory to be protected by setting the block lock bits, and finally set the otp mode by setting the wpen bit. data changes now require a hardware change. read sequence when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, follow ed by the 16-bit address. afte r the read opcode and address ar e sent, the dat a stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to pr ovide clock pulses. the address is automatically inc remented to the next higher address after each byte of data is shifted out . when the highest address is reached, the address counter r olls over to address $0000 allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 5). to read the status register, the cs line is first pulled low to select the device followed by t he 8-bit rdsr inst ruction. after the rdsr opcode is sen t, the contents of t he status register are shifted out on the so line. refer to the read status register sequence (figure 6). write sequence prior to any attempt t o write data into the device, the write enable latch (wel) must first be set by issu ing the wren instruction (figure 7). cs is first taken low, then the wren instruction is clocked into the d evice. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write op eration without taking cs high after issuing the wren instructi on, the write operation will be ignored. to write data to the eeprom memory array, the user then issues the write inst ruction followed by the 16 bit address and then the data to be written. any unused address bits are specified to be 0s . the write operation minimally takes 32 clocks. cs must go low and remain low for the duration of the operation. if the address c ounter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. for the page write operation (byte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought hi gh at any other time, the write operation will not be completed (figure 8). to write to the status regis ter, the wrsr instruction is followed by the data to be writte n (figure 9). data bits 0 and 1 must be 0. while the write is in progress following a status register or eeprom sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and rece ive an instruction. ? so pin is high impedance. ? the write enable latch is reset. ? the flag bit is reset. ? reset signal is active for t purst . data protection the following circuitry has been included to prevent inadvertent writes: ? a wren instruction must be issued to set the write enable latch. ?cs must come high at the prope r clock count in order to start a nonvolatile write cycle. x5163, x5165
10 fn8128.4 august 13, 2015 submit document feedback 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction figure 6. read status register sequence 01234567 cs si sck high impedance so figure 7. write enable latch sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3 210 20 21 22 23 24 25 26 27 28 29 30 31 654 321 0 figure 8. write sequence x5163, x5165
11 fn8128.4 august 13, 2015 submit document feedback symbol table 0123456789 cs sck si so high impedance instruction data byte 7 65432 10 10 11 12 13 14 15 figure 9. status register write sequence waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
12 fn8128.4 august 13, 2015 submit document feedback absolute maximum ratings reco mmended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . . . .-65 to +135c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150c voltage on any pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.0v to +7v d.c. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300c temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. operating specifications over operating conditions un less otherwise specified. symbol parameter test conditions limits unit min typ max i cc1 v cc write current (active) sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open 5ma i cc2 v cc read current (active) sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open 0.4 ma i sb1 v cc standby current wdt = off cs = v cc , v in = v ss or v cc , v cc =5.5v 1 a i sb2 v cc standby current wdt = on cs = v cc , v in = v ss or v cc , v cc =5.5v 50 a i sb3 v cc standby current wdt = on cs = v cc , v in = v ss or v cc , v cc =3.6v 20 a i li input leakage current v in = v ss to v cc 0.1 10 a i lo output leakage current v out = v ss to v cc 0.1 10 a v il (1) input low voltage -0.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc > 3.3v, i ol = 2.1ma 0.4 v v ol2 output low voltage 2v < v cc ? 3.3v, i ol = 1ma 0.4 v v ol3 output low voltage v cc ? 2v, i ol = 0.5ma 0.4 v v oh1 output high voltage v cc > 3.3v, i oh = C1.0ma v cc - 0.8 v v oh2 output high voltage 2v < v cc ? 3.3v, i oh = C0.4ma v cc - 0.4 v v oh3 output high voltage v cc ? 2v, i oh = C0.25ma v cc - 0.2 v v ols reset output low voltage i ol = 1ma 0.4 v capacitance t a = +25 c, f = 1mhz, v cc = 5v symbol test max. unit conditions c out (2) output capacitance (so, reset , reset) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp )6pfv in = 0v notes: 1. v il min. and v ih max. are for reference only and are not tested. 2. this parameter is periodically sampled and not 100% tested. x5163, x5165
13 fn8128.4 august 13, 2015 submit document feedback 5v output 100pf 5v 3.3k ? reset/reset 30pf 1.64k ? 1.64k ? figure 10. equivalent a.c. load circuit at 5v v cc a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x0.5 ac electrical specifications serial input timing (over operating conditions unless otherwise specified.) symbol parameter 2.7-5.5v unit min max f sck clock frequency 0 2 mhz t cyc cycle time 500 ns t lead cs lead time 250 ns t lag cs lag time 250 ns t wh clock high time 200 ns t wl clock low time 200 ns t su data setup time 50 ns t h data hold time 50 ns t ri (3) input rise time 100 ns t fi (3) input fall time 100 ns t cs cs deselect time 500 ns t wc (4) write cycle time 10 ms sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance figure 11. serial input timing x5163, x5165
14 fn8128.4 august 13, 2015 submit document feedback ac electrical specificati ons serial output timing (over operating conditions unl ess otherwise specified.) symbol parameter 2.7-5.5v unit min max f sck clock frequency 0 2 mhz t dis output disable time 250 ns t v output valid from clock low 200 ns t ho output hold time 0 ns t ro (3) output rise time 100 ns t fo (3) output fall time 100 ns notes: 3. this parameter is periodically sampled and not 100% tested. 4. t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the s elf-timed internal nonvolatile write cycle. sck cs so si msb out msbC1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag table 3. serial output timing v cc t purst t purst t r t f t rpd reset (x5163) 0 volts v trip v trip reset (x5165) table 4. power-up and power-down timing x5163, x5165
15 fn8128.4 august 13, 2015 submit document feedback reset output timing symbol parameter min typ max unit v trip reset trip point voltage, x5163-4.5a, x5163-4.5a reset trip point voltage, x5163, x5165 reset trip point voltage, x5163-2.7a, x5165-2.7a reset trip point voltage, x5163-2.7, x5165-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.92 2.63 4.75 4.5 3.0 2.7 v v th v trip hysteresis (high to l ow vs. low to high v trip voltage) 20 mv t purst power-up reset time out 100 200 280 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 100 s t r (5) v cc rise time 100 s v rvalid reset valid v cc 1v notes: 5. this parameter is periodically sampled and not 100% tested. 6. typical values not tested. reset /reset output timing symbol parameter min typ max unit t wdo watchdog time out period, wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 100 450 1 200 600 1.4 300 800 2 ms ms sec t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 100 200 300 ms cs /wdi t cst reset t wdo t rst reset t wdo t rst figure 12. cs/wdi vs. reset/reset timing x5163, x5165
16 fn8128.4 august 13, 2015 submit document feedback sck si v p v p cs t vps t vph t p t vps t vph t rp t vpo t vpo t tsu t thd v trip v cc figure 13. v trip set conditions sck si v cc v p cs t vps t vph t p t vps t vp1 t rp t vpo t vpo t tsu t thd v trip v cc figure 14. v trip reset conditions x5163, x5165
17 fn8128.4 august 13, 2015 submit document feedback v trip programming specifications: v cc = 1.7-5.5v; temperature = 0c to 70c parameter description min max unit t vps sck v trip program voltage setup time 1 s t vph sck v trip program voltage hold time 1 s t p v trip program pulse width 1s t tsu v trip level setup time 10 s t thd v trip level hold (stable) time 10 ms t wc v trip write cycle time 10 ms t rp v trip program cycle recovery period (between successive programming cycles) 10 ms t vpo sck v trip program voltage off time before next cycle 0 ms v p programming voltage 15 18 v v tran v trip programed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy ( v cc applied-v trip ) (programmed at 25c.) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [( v cc applied-v ta1 )-v trip ] (programmed at 25c.) -25 +25 mv v tr v trip program voltage rep eatability (successive program operations.) (programmed at 25c.) -25 +25 mv v tv v trip program variation after progra mming (0-75c). (programmed at 2 5c.) -25 +25 mv v trip programming parameters are periodically sampled and are not 10 0% tested. x5163, x5165
18 fn8128.4 august 13, 2015 submit document feedback figure 15. v cc supply current vs. temperature (i sb ) figure 16. t wdo vs. voltage/temperature (wd1, 0 = 1, 1) figure 17. v trip vs. temperature (programmed at 25c) figure 18. t wdo vs. voltage/temperature (wd1, 0 = 1, 0) figure 19. t purst vs. temperature figure 20. t wdo vs. voltage/temperature (wd1, 0 0 = 0, 1) 18 16 14 12 10 8 6 4 2 0 watchdog timer on (v cc = 5v) watchdog timer on (v cc = 5v) watchdog timer off (v cc = 3v, 5v) -40 25 90 temp (c) isb (a) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1.7 2.4 3.1 3.8 4.5 5.2 90c 25c -40c reset (seconds) voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 025 85 voltage temperature v trip = 5v v trip = 3.5v v trip = 2.5v 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 1.7 5.2 reset (seconds) voltage 2.4 3.1 3.8 4.5 90c 25c -40c 200 195 190 185 180 175 170 165 160 -40 25 90 degrees c 205 time (ms) 90c 25c -40c 200 195 190 185 180 175 170 165 160 205 reset (seconds) voltage 1.7 5.2 2.4 3.1 3.8 4.5 x5163, x5165
19 all intersil u.s. products are m anufactured, assembled and test ed utilizing iso9001 quality systems. intersil corporations quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products , see www.intersil.com fn8128.4 august 13, 2015 submit document feedback about intersil intersil corporation is a leading provider of innovative power management and precision analog solutions. the company's produc ts address some of the largest marke ts within the industrial and i nfrastructure, mobile computing and high-end consumer markets. for the most updated datasheet, application no tes, related documentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggesti ons for improving this datashe et by visiting www.intersil.com/ask . reliability reports are also a vailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision . date revision change august 13, 2015 fn8128.4 - ordering information table on page 2. - added revision history beginning with rev 1. - added about intersil verbiage. - updated pod mdp0027 to latest rev ision changes are as follow: added dimensions (inches) to table. - updated pod mdp0031 to latest rev ision changes are as follow: added dimensions (inches) to table. - updated pod m14.173 to most cu rrent version changes are as fo llow: updated drawing to remove table and added land pattern. x5163, x5165
20 fn8128.4 august 13, 2015 submit document feedback x5163, x5165 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail x c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150) so16 (0.300) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ? 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ? 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ? 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ? 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ? 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ? 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ? 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ? 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions o f 0.006 maximum per side are n ot included. 2. plastic interlead protrusions of 0.010 maximum per side are not included. 3. dimensions d and e1 are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994
21 fn8128.4 august 13, 2015 submit document feedback x5163, x5165 plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions o f 0.010 maximum per side are n ot included. 2. plastic interlead protrusions of 0.010 maximum per side are not included. 3. dimensions e and ea are measu red with the leads constrained p erpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
22 fn8128.4 august 13, 2015 submit document feedback x5163, x5165 package outline drawing m14.173 14 lead thin shrink small outline package (tssop) rev 3, 10/09 detail "x" side view typical recommended land pattern top view b a 17 8 14 c plane seating 0.10 c 0.10 c b a h pin #1 i.d. mark 5.00 0.10 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 5 2 3 1 3 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (1.45) (5.65) (0.65 typ) (0.35 typ) detail "x" 1. dimension does not include mold flash, protrusions or gate b urrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. dimension does not include interlead flash or protrusion. i nterlead flash or protrusion shall not exceed 0.25 per side. 3. dimensions are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. dimension does not include dambar protrusion. allowable prot rusion shall be 0.80mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. 6. dimension in ( ) are for reference only. 7. conforms to jedec mo-153, variation ab-1. notes: end view

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